Semiconductor memory device and method for manufacturing same
US7187607B2 · kind B2 · utility
80Cited by
1References
9Claims
0Family size
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Key dates
| Filing date | Oct 6, 2004 |
| Grant date | Mar 6, 2007 |
| Priority date | — |
| Expiry date | Mar 25, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/78
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
At first, failed cells are repaired using row redundancy or column redundancy as done in the past and then, for the remaining failed cells that cannot be repaired by row or column redundancy, by increasing the number of refreshes greater than that of normal cells, it is possible to repair more failed cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.