Flash/dynamic random access memory field programmable gate array
US7187610B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 10, 2006 |
| Grant date | Mar 6, 2007 |
| Priority date | — |
| Expiry date | Jul 10, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0441
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for providing a circuit for selectively interconnecting N pairs of nodes in an integrated circuit device comprising: providing a memory array having a plurality of wordlines and a plurality of bitlines; providing a plurality of dynamic random access memory wordlines; providing a separate switch for each pair of nodes in the integrated circuit, each switch associated with a unique combination of one of the plurality of bitlines and one of the plurality of dynamic random access memory wordlines, each switch including a refresh transistor and a switching transistor; and providing an address decoder having at least N distinct states for supplying signals to the plurality of wordlines and the plurality of dynamic random access memory wordlines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.