Clock domain crossing FIFO
US7187741B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2001 |
| Grant date | Mar 6, 2007 |
| Priority date | — |
| Expiry date | Mar 5, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0008
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method and arrangement of passing data from a source clock domain to a non-synchronous receive clock domain are provided. A first processing circuit, located in the source clock domain, links write-address information with the data, and a clock generator generates a transmit clock signal in the source clock domain synchronous with a source clock. The first processing circuit transmits the clock signal and the data with the linked write-address information to a second processing circuit in the receive clock domain. In the receive clock domain, the second processing circuit writes the data at an address designating a storage element corresponding to the linked write-address information. The second processing circuit clocks the data into the storage element synchronous with the accompanying transmit clock signal responsive to a write enable signal from the source clock domain, and reads the data out of the storage element synchronous with a receive domain clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.