Simulation monitors based on temporal formulas
US7188061B2 · kind B2 · utility
3Cited by
1References
28Claims
0Family size
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Key dates
| Filing date | Jul 15, 2002 |
| Grant date | Mar 6, 2007 |
| Priority date | — |
| Expiry date | Sep 15, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3323
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for design verification includes receiving a software model of a design of a system under evaluation, and providing a property, which is dependent on a specified variable having a predefined range of values. The property applies to all states of the system for any selected value among the values of the variable within the predefined range. The property is processed so as to generate a checker program for detecting a violation of the property. A simulation of the system is then run using the software model together with the checker program.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.