Method for implementing dynamic virtual lane buffer reconfiguration
US7188198B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 11, 2003 |
| Grant date | Mar 6, 2007 |
| Priority date | — |
| Expiry date | Feb 25, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/35
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method, apparatus and computer program product are provided for implementing dynamic Virtual Lane buffer reconfiguration in a channel adapter. A first register is provided for communicating an adapter buffer size and allocation capability for the channel adapter. At least one second register is provided for communicating a current port buffer size and one second register is associated with each physical port of the channel adapter. A plurality of third registers is provided for communicating a current VL buffer size, and one third register is associated with each VL of each physical port of the channel adapter. The second register is used for receiving change requests for adjusting the current port buffer size for an associated physical port. The third register is used for receiving change requests for adjusting the current VL buffer size for an associated VL.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.