Method and apparatus for embedding an additional layer of error correction into an error correcting code
US7188295B2 · kind B2 · utility
10Cited by
7References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 14, 2003 |
| Grant date | Mar 6, 2007 |
| Priority date | — |
| Expiry date | Apr 25, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/2954
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method of embedding an additional layer of error correction into an error correcting code, where information is encoded into code words that are arranged in columns of a code block. The method includes reducing the length of each row of the code block by adding row symbols together according to a predetermined adding rule resulting in a reduced code block; encoding the shortened rows of the reduced code block using a horizontal error correcting code to obtain horizontal parities; and embedding the horizontal parities as additional layer in the error correcting code.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.