Restricted scan reordering technique to enhance delay fault coverage
US7188323B2 · kind B2 · utility
7Cited by
1References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 15, 2004 |
| Grant date | Mar 6, 2007 |
| Priority date | — |
| Expiry date | May 12, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318544
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Disclosed is a method and apparatus for improved delay fault testing by optimizing the order of scan cells in a scan chain. The order of the scan cells is determined by using a cost value for an order of scan cells, the cost value being computed from costs assigned to orderings of individual pairs of scan cells. These costs can be based on the number of faults that are untestable when the pair of scan cells are placed consecutively in the scan chain. The disclosed techniques allow for enhanced delay fault coverage by rearranging scan flip-flops without increasing routing overhead.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.