Multiple test bench optimizer
US7191112B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 26, 2001 |
| Grant date | Mar 13, 2007 |
| Priority date | — |
| Expiry date | Apr 4, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Test benches, simulations, and scripts are invoked in parallel for testing multiple points in a circuit being synthesized in an Analog Mixed Signal environment. A simulation system for simultaneously optimizing performance characteristics in circuit synthesis uses a set of design parameters. At least one circuit model is used to incorporate the set of design parameters, each circuit model adapted to model a portion of the circuit pertaining to a performance characteristic. At least one analysis test bench is then connected to each circuit model. Each analysis test bench is adapted to model circuitry external to the circuit and control the type of analysis to be performed for each performance characteristic of the circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.