Packet prioritization systems and methods using address aliases
US7191249B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 2, 2002 |
| Grant date | Mar 13, 2007 |
| Priority date | — |
| Expiry date | Dec 3, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/90
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A switch fabric includes input links, output links, and at least one switching element. The input links are configured to receive data items that include destination addresses. At least some of the data items have different priority levels. The output links are configured to output the data items. Each of the output links is assigned multiple ones of the destination addresses. Each of the destination addresses corresponds to one of the priority levels. The switching element(s) is/are configured to receive the data items from the input links and send the data items to ones of the output links without regard to the priority levels of the data items.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.