High-throughput UART interfaces
US7191262B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 3, 2003 |
| Grant date | Mar 13, 2007 |
| Priority date | — |
| Expiry date | May 27, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04W76/10
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A modified universal asynchronous receiver transmitter (UART) device is provided with an auxiliary high speed parallel channel using supplementary FIFO buffers for the exchange of data. The auxiliary parallel channel is separate from the normal lower speed serial channel which is retained in unmodified form. The retained serial channel provides full compatibility with and support for the National Semiconductor 16550 standard, while the auxiliary parallel channel allows for rapid transfer of large data blocks, such as is needed for a PCMCIA wireless data card for example. The key advantages of this approach lie both in the data transfer speed and in the reduced amount of development time needed to implement a UART interface for communicating between a host computer and a new subsystem. This is because all the UART functions, except large volume data transfer, can be carried out over the standard serial channel using standard device drivers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.