JTAG and boundary scan automatic chain selection
US7191265B1 · kind B1 · utility
5Cited by
13References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 29, 2003 |
| Grant date | Mar 13, 2007 |
| Priority date | — |
| Expiry date | Oct 31, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318572
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A printed circuit board (PCB) may be used in a first mode where boundary scan techniques are used to externally program and/or test devices on the PCB, or a second mode where an internal source programs devices using boundary scan techniques. In one implementation, there is also additional flexibility to include or skip devices in a boundary scan chain and to accommodate non-scan related functions for pins used for scanning. These various modes of operation may be selected by activating and deactivating buffers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.