Memory control device for controlling transmission of data signals
US7191302B2 · kind B2 · utility
16Cited by
6References
14Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 25, 2003 |
| Grant date | Mar 13, 2007 |
| Priority date | — |
| Expiry date | Feb 21, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1689
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An ASIC that includes a data latch for latching a data signal from a CPU and a buffer for holding the data signal output from the latch. When presently latched signal is at a higher electric potential than the data signal outputted to the buffer, that is, when then the data signal from the CPU changes from an H state to an L state, then the ASIC delays output of the buffered data signal to a memory (a pair of DIMMs) for one or more periods of the synchronization clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.