Method and intelligent slave device transfer control unit for implementing seamless error resumption in a shared memory bus structure
US7191366B2 · kind B2 · utility
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11References
10Claims
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Key dates
| Filing date | Feb 26, 2004 |
| Grant date | Mar 13, 2007 |
| Priority date | — |
| Expiry date | Dec 3, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0793
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus are provided for implementing seamless error resumption in a shared memory bus structure. Controls and data are stored for each read operation and each write operation. Each read operation and each write operation is monitored to determine when an error has occurred for either a read operation or a write operation. When an error has occurred for the read operation or the write operation, the error is suppressed and the stored controls and data are gated to continue the read operation or the write operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.