Magnetic memory with error correction coding
US7191379B2 · kind B2 · utility
114Cited by
10References
28Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 10, 2003 |
| Grant date | Mar 13, 2007 |
| Priority date | — |
| Expiry date | Apr 12, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2211/109
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present invention are implemented in memory systems. In one embodiment, the memory comprises an array of memory cells and a control circuit. The control circuit is configured to read error correction coded data from the array of memory cells, provide error correction code decoding to selected error correction coded data and discard unused error correction code parity data of unselected error correction coded data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.