System and method for optimizing iterative circuit for cyclic redundancy check (CRC) calculation
US7191383B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 28, 2003 |
| Grant date | Mar 13, 2007 |
| Priority date | — |
| Expiry date | Apr 1, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6508
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system for generating CRC code words associated with data ranging up to w-bytes in width. The system is an iterative approach for providing a CRC calculation circuitry with the CRC calculation being subdivided into a blocks with selectable bus widths which blocks can be cascaded to provide calculation for a parallel bus width of any arbitrary number of bytes. The circuitry includes a first plurality of serially coupled code-generation blocks each for generating a CRC value based on data input to each block; a second plurality of parallel coupled code-generation blocks each for generating a CRC value based on data inputs, and, a device for selecting particular CRC code generation blocks in the first and second pluralities to be included in a CRC calculation based on the data input such that any number of data input bytes may be processed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.