Method for mapping a logic circuit to a programmable look up table (LUT)
US7191427B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 23, 2004 |
| Grant date | Mar 13, 2007 |
| Priority date | — |
| Expiry date | Mar 23, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The method for mapping a logic circuit to a plurality of interconnectable, programmable look up tables (LUT) elements includes forming logic element groups including individual logic elements and/or previously formed logic element groups that are capable of being accommodated within the fanin and/or fanout capacity of a target LUT. The method further includes mapping the formed logic element group to the target LUT, and repeating the process for forming logic element groups and mapping to target LUTs for the entire network in a manner such that at each stage only the unmapped logic element/elements and mapped logic element groups of the previous stage are considered for mapping.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.