Floating gate transistors
US7193264B2 · kind B2 · utility
58Cited by
5References
15Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 28, 2003 |
| Grant date | Mar 20, 2007 |
| Priority date | — |
| Expiry date | Oct 28, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A floating gate MOS transistor comprises one or more control gates, an active channel, and at least one floating gate disposed between the control gate(s) and the active channel. First and second non-linear resistances couple the floating gate to first and second control voltage sources respectively, the non-linear resistances forming a voltage divider network which sets the operating voltage of the floating gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.