Dynamic logic circuit incorporating reduced leakage state-retaining devices
US7193446B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 18, 2004 |
| Grant date | Mar 20, 2007 |
| Priority date | — |
| Expiry date | Jun 15, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0016
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A dynamic logic circuit incorporating reduced leakage state-retaining devices reduces power consumption of processors and other systems incorporating dynamic circuits. A keeper circuit provides a low leakage retention of the state of the output stage of the dynamic circuit so that an output circuit foot device can be disabled except when required for a transition in the output of the dynamic circuit. The keeper circuit includes a transistor having a smaller area than a corresponding transistor in the output circuit, thus reducing leakage through the gate of the output circuit when the keeper circuit is holding the output and the output circuit foot device is disabled. A self-clocked control of the output circuit foot device can be provided via a delayed version of the dynamic logic gate output, or may be provided by an external control circuit that generates a delayed version of the precharge clock or a multi-cycle signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.