Load sensing buffer circuit with controlled switching current noise (di/dt)
US7193450B1 · kind B1 · utility
1Cited by
10References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 2, 2004 |
| Grant date | Mar 20, 2007 |
| Priority date | — |
| Expiry date | Feb 14, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/167
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A load sensing buffer circuit for providing a buffered clock signal with controlled switching current noise (di/dt) in which the input clock signal is selectively gated to provide successively generated source and sink current components as part of the buffered output signal, with the timing of such current components being dependent upon load capacitance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.