System and method of oversampling high speed clock/data recovery
US7194057B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 21, 2005 |
| Grant date | Mar 20, 2007 |
| Priority date | — |
| Expiry date | Dec 21, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0337
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A system and method of high speed clock/data recovery, which is used to recover the high speed clock/data through oversampling technique, wherein the internal clock with frequency lower than the high speed data is used for data recovery. Only three clocks are used in the digital circuit without involving all the oversampling clock phases to make the design timing complicated and critical. The system and method provide a simple clock structure to implement the digital circuit of high speed clock/data recovery in a robust and easy way. Furthermore a phase selection mechanism which decides the clock phase of the high speed data is provided as well.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.