System and method for producing functions for generating pseudo-random bit sequences
US7194496B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 2, 2003 |
| Grant date | Mar 20, 2007 |
| Priority date | — |
| Expiry date | Mar 3, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/584
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a system and method for producing functions for generating pseudo-random bit sequences, an extended shift register (ESR) is formed. Each bit in the ESR is shifted to a next higher bit and the lowest-order bit is replaced with an EXCLUSIVE-OR operation of at least two other bits in the ESR. A plurality of bit equations is generated. For each bit equation, a bit in the ESR is replaced with an AND operation between shifted contents of the ESR and one of a plurality of first bit masks that isolate the bit. Each of the plurality of bit equations is combined. Shifts of the same shift distance are merged. Redundant bit masks are removed. Bit masks are transformed into bit masks comprising a sequence of zero bits and one bits. Bit masks are replaced with bit shift operations to form a function for generating the pseudo-random bit sequences.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.