Hardware-based accelerator for time-domain scientific computing
US7194497B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 15, 2002 |
| Grant date | Mar 20, 2007 |
| Priority date | — |
| Expiry date | Jan 6, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/23
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention is directed to an apparatus and methods that facilitate implementation of a practical Finite-Difference-Time-Domain (FDTD) hardware accelerator. The apparatus and methods of the present invention increase speed, reduce memory requirements, and/or simplify a FDTD hardware implementation. This is accomplished by providing one, some, or all of the following: a reformulated FDTD method to simplify the hardware implementation; a memory look-up table (MLUT) to decrease memory requirements; customized, floating-point arithmetic units optimized for speed to decrease execution time; a memory switching unit (MSU) that coordinates multiple memory reads and writes from/to multiple random access memories (RAMs) to simplify control; a data dependence unit (DDU) that determines all dependencies associated with a given calculation to simplify control; and/or a control unit based on a global counter to simplify control.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.