System and method for low overhead message passing between domains in a partitioned server
US7194517B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 21, 2002 |
| Grant date | Mar 20, 2007 |
| Priority date | — |
| Expiry date | May 17, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L69/329
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A system and method for passing messages between domains with low overhead in a multi-node computer system. A CPU node in a sending domain issues a request to a memory node in a receiving domain using memory-mapped input/output window. This causes the message to be transmitted to a coherent space of the receiving domain. All messages are cache-line in size. A small portion of each cache line, cyclic counter field, is overwritten before the cache line is written in the coherent address space of the receiving domain. A massaging driver polls the cyclic count field of the cache line in the processor cache to determine when the next message is written in the coherent address space of the receiving domain. This allows the CPU to detect when the last received message is written into the coherent address space of the receiving domain without generating transactions on CPU interface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.