Method and apparatus for implementing cache state as history of read/write shared data
US7194586B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 20, 2002 |
| Grant date | Mar 20, 2007 |
| Priority date | — |
| Expiry date | Mar 12, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0831
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus are provided for implementing a cache state as history of read/write shared data for a cache in a shared memory multiple processor computer system. An invalid temporary state for a cache line is provided in addition to modified, exclusive, shared, and invalid states. The invalid temporary state is entered when a cache releases a modified cache line to another processor. The invalid temporary state is used to enable effective optimizations within cache coherent symmetric multiprocessor (SMP) systems of an SMP caching hierarchy with distributed caches with different caching coherency traffic profiles for both commercial and technical workloads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.