System and method using embedded microprocessor as a node in an adaptable computing machine
US7194598B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 26, 2004 |
| Grant date | Mar 20, 2007 |
| Priority date | — |
| Expiry date | Oct 30, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/8007
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides an adaptive computing engine (ACE) that includes processing nodes having different capabilities such as arithmetic nodes, bit-manipulation nodes, finite state machine nodes, input/output nodes and a programmable scalar node (PSN). In accordance with one embodiment of the present invention, a common architecture is adaptable to function in either a kernel node, or k-node, or as general purpose RISC node. The k-node acts as a system controller responsible for adapting other nodes to perform selected functions. As a RISC node, the PSN is configured to perform computationally intensive applications such as signal processing. The present invention further provides an interconnection scheme so that a plurality of ACE devices operates under the control of a single k-node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.