High availability synchronization architecture
US7194652B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 29, 2002 |
| Grant date | Mar 20, 2007 |
| Priority date | — |
| Expiry date | Jun 11, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L69/329
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A “high availability” system comprises one or more switches under the control of multiple control processors (“CPs”). One of the CPs is deemed to be “active,” while the other CP is kept in a “standby” mode. Each CP generally has the same software load including a fabric state synchronization (“FSS”) facility. The FSSs of each CP communicate with each other. The state information pertaining to an active “image” is continuously provided to a standby copy of the image (“standby image”). The CPs' FSSs perform the function of synchronizing the standby image to the active image. The state information generally includes configuration and operational parameters and other information regarding the active image. By keeping the standby image synchronized to the active image, the standby image can be rapidly transitioned to the active mode if the active image experiences a fault and continue where the previous active image left off.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.