CRC verification apparatus with constant delay and method thereof
US7194672B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 25, 2003 |
| Grant date | Mar 20, 2007 |
| Priority date | — |
| Expiry date | Mar 28, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/091
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for detecting errors in received data and transferring only error-free data in data communications are provided. In the cyclic redundancy check (CRC) verification apparatus and method having a constant delay, irrespective of the length of a received data frame, input and output processing delay of received data is made to be constant. The CRC verification apparatus having constant delay comprises an input control unit which stores the start address of an input data frame in a memory storing the input data frame, and stores a CRC verification result in the start address location; and an output control unit which after a predetermined constant time passes from the start address, reads an input data frame and if the CRC verification result is normal, output the read data frame. The apparatus and method make the time taken for receiving a data frame, constant irrespective of the received data frame, while CRC verification is performed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.