High level synthesis method and high level synthesis apparatus
US7194724B2 · kind B2 · utility
10Cited by
1References
29Claims
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Key dates
| Filing date | Nov 16, 2004 |
| Grant date | Mar 20, 2007 |
| Priority date | — |
| Expiry date | Sep 9, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
First of all, the number of referencing of a variable described in a behavior level circuit is calculated. Next, a bit width of the variable is extracted, and a plurality of memories capable of data transferring of the extracted bit width are selected. Next, a sum of a frequency of memory access for each of the selected plurality of memories when the variable is allocated thereto is calculated based on the number of referencing and the bit width of the variable. After that, as a target for allocating the variable, a memory that minimizes the calculated sum of the frequency of the memory access is selected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.