Nonvolatile semiconductor memory device having trench-type isolation region, and method of fabricating the same
US7196370B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 26, 2004 |
| Grant date | Mar 27, 2007 |
| Priority date | — |
| Expiry date | Apr 27, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
Abstract
A nonvolatile semiconductor memory device includes a memory cell array region including a plurality of NAND cells, each NAND cell having a plurality of memory cell transistors, and which are arranged in series, and a plurality of select transistors. A trench-type isolation region is formed between columns in the array of the NAND columns. The trench-type isolation region is formed in self-alignment with end portions of the channel region and a floating gate of the memory cell transistor, formed in self-alignment with the end portion of a channel region of the select transistor, and has a recess formed in at least the upper surface between the floating gates of the memory cell transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.