Electrostatic-protection dummy transistor structure
US7196378B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 29, 2004 |
| Grant date | Mar 27, 2007 |
| Priority date | — |
| Expiry date | Mar 29, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
Abstract
A semiconductor apparatus where output and protection transistors are different in transistor structure, and where, even when breakdown in the output transistor occurs earlier than in the protection transistor, an ESD surge current does not concentrate in the output transistor inferior in ESD resistance. Formed in its output circuit, where the drain and source of a first-conductivity-type, e.g. NMOS, output transistor 11 are connected respectively to an output electrode and to ground, is an NMOS protection transistor 10 of which the drain and source are connected respectively to the drain and source of the NMOS output transistor 11 and of which the gate is directly connected to a second-conductivity-type layer, a P-well 22, under the gate electrode of the NMOS output transistor 11. By this means, an electrostatic surge does not concentrate in the NMOS output transistor 11.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.