Semiconductor structure for isolating integrated circuits of various operation voltages
US7196392B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 24, 2005 |
| Grant date | Mar 27, 2007 |
| Priority date | — |
| Expiry date | Aug 25, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/854
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure includes an isolation ring disposed on a semiconductor substrate, surrounding first and second circuit areas. A buried isolation layer is continuously extended through the first circuit area and the second circuit area, in the semiconductor substrate. The buried isolation layer interfaces with the isolation ring, thereby isolating the first and second circuit areas from a backside bias of the semiconductor substrate. An ion enhanced isolation layer separates the first well in the first circuit area and the second well in the second circuit areas from the isolation ring and the buried isolation layer, thereby preventing punch-through between the wells of the circuit areas and the buried isolation layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.