Resistor integration structure and technique for noise elimination
US7196398B2 · kind B2 · utility
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2References
9Claims
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Key dates
| Filing date | Mar 4, 2005 |
| Grant date | Mar 27, 2007 |
| Priority date | — |
| Expiry date | Mar 4, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01C7/18
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A method of preventing contact noise in a SiCr thin film resistor includes performing in situ depositions of a SiCr layer and then a TiW layer on a substrate without breaking a vacuum between the depositions, to prevent formation of any discontinuous oxide between the SiCr layer and the TiW layer. The SiCr and TiW layers are patterned to form a predetermined SiCr thin film resistor pattern and a TiW resistor contact pattern on the SiCr thin film resistor, and a metallization layer is provided to contact the TiW forming the resistor contact pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.