Resolver arrangement
US7196643B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 3, 2006 |
| Grant date | Mar 27, 2007 |
| Priority date | — |
| Expiry date | Feb 3, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/645
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A resolver arrangement that is inexpensive and yet offers high resolution and high noise rejection includes a carrier signal generator and two processing channels each of which has an analog input connected a different one of the stator coils and a channel output. Each of the processing channels includes a sigma-delta modulator with an output that supplies a bit-stream representative of an analog input signal received from a respective stator coil. Each channel also includes a first digital filter that receives the bit-stream from the sigma-delta modulator and converts the bit-stream to intermediate digital data-words. In addition, each channel has a digital synchronous demodulator that demodulates the intermediate digital data-words in synchronism with the carrier signal providing demodulated data-words. Finally, each channel has a second digital filter that averages the demodulated data-words and supplies digital output data-words on the channel output, the carrier signal being suppressed in the output data-words.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.