Methods and apparatuses for reducing infant mortality in semiconductor devices utilizing static random access memory (SRAM)
US7197670B2 · kind B2 · utility
25Cited by
6References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 31, 2003 |
| Grant date | Mar 27, 2007 |
| Priority date | — |
| Expiry date | Jun 29, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1032
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In accordance with various embodiments of the present invention, a cache-equipped semi-conductor device is provided with enhanced error detection logic to detect a first location-independent error within an area of the cache memory and prevent further use of the area if the error is determined to be the second consecutive error associated with a common area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.