Floorplan visualization method using gate count and gate density estimations
US7197735B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 15, 2004 |
| Grant date | Mar 27, 2007 |
| Priority date | — |
| Expiry date | May 13, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/392
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for floorplan visualization comprising the steps of (A) receiving design information for an integrated circuit design comprising one or more subsystems, (B) generating one or more gate count estimates for the one or more subsystems of the integrated circuit design, (C) generating one or more gate density estimates for gates of the one or more subsystems mapped to one or more programmable areas of a programmable platform device and (D) generating a visual representation of one or more area estimations for each of the one or more subsystems based on the one or more gate count estimates and the one or more gate density estimates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.