Techniques for placing dummy features in an integrated circuit based on dielectric pattern density
US7197737B1 · kind B1 · utility
8Cited by
4References
17Claims
0Family size
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Key dates
| Filing date | Dec 17, 2004 |
| Grant date | Mar 27, 2007 |
| Priority date | — |
| Expiry date | Apr 29, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a dummy pattern having a plurality of dummy features (e.g., waffles) are employed to help achieve a relatively planar surface by chemical-mechanical planarization (CMP). The dummy features are placed based on a dielectric pattern density of a region of an integrated circuit. The dummy features may be added to the design of the integrated circuit using a one pass or two pass approach. The dummy features in a second pass may be fragmented using an AndNot algorithm, for example.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.