Method for making a neo-layer comprising embedded discrete components
US7198965B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 14, 2006 |
| Grant date | Apr 3, 2007 |
| Priority date | — |
| Expiry date | Feb 14, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/162
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stackable neo-layer comprising one or more embedded discrete electrical components is provided. A plurality of conductive traces, some of which terminate at a peripheral edge of the layer, are formed on sacrificial substrate in a series of process steps and discrete electrical components such as thick film components or wire bonded components are attached thereto. An under-bump metal process step is disclosed and provides for solder attachment at desired contact pad locations. The layer is encapsulated in a potting material and thinned to provide a thin, stackable layer. When assembled into a stack of layers, the electrically conductive traces terminating at the edge of the layer can be electrically connected by means of electroplating using a T-connect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.