Voltage regulator output stage with low voltage MOS devices
US7199567B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 9, 2004 |
| Grant date | Apr 3, 2007 |
| Priority date | — |
| Expiry date | Feb 28, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F1/575
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
Circuits and methods to provide an LDO output stage implemented with low-voltage devices and still allowing higher voltage levels have been achieved. The output stage has been built using two low voltage MOS devices in series. During the time the regulator is in active mode the second MOS device acts as a small resistor in series to the pass device. During power down this second device actively protects the MOS pass device and itself from high voltage stress levels. This is achieved by a robust regulating mechanism that compensates leakage currents. These leakage currents normally determine the different potentials of the output stage during power down. Although the second transistor presents a resistive obstacle during active mode the total chip area required is smaller compared to a single pass device tolerating e.g. 5 Volts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.