High-speed differential logic multiplexer
US7199619B2 · kind B2 · utility
2Cited by
4References
32Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 20, 2004 |
| Grant date | Apr 3, 2007 |
| Priority date | — |
| Expiry date | Sep 20, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/693
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit for a high speed digital multiplexer has an active load circuit connected to an output of the digital multiplexer. The active load circuit loads the multiplexer output with a transimpedance stage with low input resistance to reduce the RC time constant at the multiplexer output. The active load circuit may be based on two active devices connected to the multiplexer output so as to form a differential cascode circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.