Phase locked loop system capable of deskewing
US7199624B2 · kind B2 · utility
2Cited by
8References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2003 |
| Grant date | Apr 3, 2007 |
| Priority date | — |
| Expiry date | Apr 30, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/04
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system is provided that includes a phase lock loop component to output a first signal based on a reference clock signal and a feedback clock signal. A clock distribution network may distribute a clock signal based on the first signal output from the phase lock loop component. Additionally, a delay lock loop component may deskew a signal and adjust the clock signal distributed by the clock distribution network.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.