Bi-directional double NMOS switch
US7199640B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 22, 2003 |
| Grant date | Apr 3, 2007 |
| Priority date | — |
| Expiry date | Oct 16, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/063
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A semiconductor switch comprises two NMOS transistors coupled in an anti-series arrangement, and a gate control circuit coupled to both gates of the NMOS transistors. Both drains of the NMOS transistors are interconnected, and the gate control circuit is coupled to the drains interconnection. The required chip area is halved compared to prior art switches. Pumping the gates to higher voltages may cause a further reduction of the sizes of the NMOS transistors. In addition, advantageously, a large range of input and output voltages can be allowed between the sources of the NMOS transistors, whereby the sources act as input and output respectively of the switch, thus allowing application of the switch in a broad technical field.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.