Method and system for providing adaptive timing recovery for low power application
US7200189B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 11, 2002 |
| Grant date | Apr 3, 2007 |
| Priority date | — |
| Expiry date | Apr 7, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0029
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A system for providing adaptive timing recovery is provided. In an exemplary embodiment, the system includes a fractional resampler, an error function module and a loop filter, arranged collectively to form a timing recovery loop. In an initial mode, the error function module compares the output of the fractional resampler with a reference signal to determine an error, if any. An error signal is generated accordingly based on the error. The error signal is then provided to the loop filter allowing the loop filter to generate a correction signal. The correction signal is provided to the fractional resampler to allow the fractional resampler to generate an output which minimizes the error. When the error function module determines that the error is within an acceptable range, i.e., a timing lock is achieved, the system goes into a steady mode. In the steady mode, the error function module is directed to execute at a slower rate. By executing at a slower rate, the error function module is able to operate at a reduced level of power consumption.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.