Reduction of dynamic DC offsets in a wireless receiver
US7200372B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 3, 2004 |
| Grant date | Apr 3, 2007 |
| Priority date | — |
| Expiry date | Feb 10, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B1/30
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A gain control system in a Direct Conversion Receiver or similar receiver, includes an automatic gain control circuit which determines whether a low noise amplifier, which amplifies signals from an antenna prior to mixing with signals from a local oscillator, should be set to a high gain or a low gain. The output of the mixer is analyzed by a blocker detect circuit to determine whether a blocker signal is present. Based on the presence of a blocker signal and the power level of the useful signal, the gain of the low noise amplifier may be reduced from the high gain to an intermediate gain in order to reduce self mixing between the radio frequency and local oscillator ports of the mixer, which may lead to dynamic DC offsets.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.