Memory access system providing increased throughput rates when accessing large volumes of data by determining worse case throughput rate delays
US7200690B2 · kind B2 · utility
1Cited by
1References
16Claims
0Family size
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Key dates
| Filing date | Apr 22, 2004 |
| Grant date | Apr 3, 2007 |
| Priority date | — |
| Expiry date | Jun 10, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Enhancing the throughput rate of a memory access system by using store and forward buffers (SFB) in combination with a DMA engine. According to an aspect of the present invention, the worst case throughput rate (without use of SFBs) is computed, and maximization factor equaling a desired throughput rate divided by the worst case throughput rate is computed. A number of SFBs is determined as equaling one less than the maximization factor. By placing the SFBs at appropriate locations in the data transfer path, the desired throughput rate may be attained when transferring large volumes of data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.