System and method for processing system management interrupts in a multiple processor system
US7200701B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 26, 2004 |
| Grant date | Apr 3, 2007 |
| Priority date | — |
| Expiry date | Mar 31, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for processing system management interrupts in multiple processor systems is disclosed. In one embodiment, a method for processing a system management interrupt (SMI) in an information handling system including, for each processor, identifying whether the processor is an interrupt handling processor assigned to perform processing tasks necessary for resolving the SMI or a non-interrupt handling processor not assigned to perform the processing tasks necessary for resolving the SMI. The method further including, for each non-interrupt handling processor, setting the non-interrupt handling processor into a wait for Start-up Inter-Processor Interrupt (SIPI) mode. The method further including, for the interrupt handling processor, performing the processing tasks necessary for resolving the SMI such that upon entry into a SMI handler the interrupt handling processor enters and exits the SMI handler without synchronization with the non-interrupt handling processors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.