High-performance hybrid processor with configurable execution units
US7200735B2 · kind B2 · utility
19Cited by
21References
71Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 10, 2002 |
| Grant date | Apr 3, 2007 |
| Priority date | — |
| Expiry date | May 22, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/7867
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A new general method for building hybrid processors achieves higher performance in applications by allowing more powerful, tightly-coupled instruction set extensions to be implemented in reconfigurable logic. New instructions set configurations can be discovered and designed by automatic and semi-automatic methods. Improved reconfigurable execution units support deep pipelining, addition of additional registers and register files, compound instructions with many source and destination registers and wide data paths. New interface methods allow lower latency, higher bandwidth connections between hybrid processors and other logic.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.