Error checking and correcting for content addressable memories (CAMs)
US7200793B1 · kind B1 · utility
5Cited by
4References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 22, 2002 |
| Grant date | Apr 3, 2007 |
| Priority date | — |
| Expiry date | Dec 15, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Error checking and correcting (ECC) is performed on data held in a content addressable memory. An error check circuit receives words from a memory circuit or circuits, generates an error status and generates a corrected value when appropriate. A control circuit sequences through each of the words of the memory circuit(s), periodically reads from the memory circuit the next word in the sequence and provides the next word to the error check circuit. The bandwidth consumed by the periodic error check phase can be controlled by adjusting the interval between reads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.