Circuits with modular redundancy and methods and apparatuses for their automated synthesis
US7200822B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 14, 2004 |
| Grant date | Apr 3, 2007 |
| Priority date | — |
| Expiry date | Apr 19, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Digital circuits with time multiplexed redundancy and methods and apparatuses for their automated designs generated from single-channel circuit designs. At least one embodiment of the present invention includes a digital circuit which detects or corrects transitory upsets through time-multiplexed resource sharing. In one embodiment of the present invention, time-multiplexed resource sharing is used to reduce the die area for implementing modular redundancy. One embodiment of the present invention automatically and efficiently synthesizes multi-channel hardware for time-multiplexed resource sharing by automatically generating a time-multiplexed design of multi-channel circuits from the design of a single-channel circuit, in which at least a portion of the channels are allocated for modular redundancy.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.