Dynamic logic circuit apparatus and method for reducing leakage power consumption via separate clock and output stage control
US7202705B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 18, 2004 |
| Grant date | Apr 10, 2007 |
| Priority date | — |
| Expiry date | Apr 5, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0966
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A dynamic logic circuit apparatus and method for reducing leakage power consumption via separate clock and output stage control reduces power consumption of processors and other systems incorporating dynamic circuits. The power control signal may be a delayed version of the logic clock and turns on the output inverter foot device after the dynamic node has had sufficient time to evaluate, providing a fast evaluate time and reducing leakage through the inverter input when the foot device is off. Alternatively, a coarsely timed static power control signal may be used to control the inverter foot devices. The drains of the inverter foot devices can be commonly connected across multiple circuits, reducing the foot device total area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.