Efficient implementation of a read scheme for multi-threaded register file
US7203100B2 · kind B2 · utility
26Cited by
3References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 21, 2005 |
| Grant date | Apr 10, 2007 |
| Priority date | — |
| Expiry date | May 6, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3851
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-threaded memory system including a plurality of entries, each one of the plurality of entries including a plurality of threads, each one of the plurality of threads including an active cell and a shared read cell. The shared read cell has an output coupled to a read bit line and a corresponding plurality of inputs coupled to an output of the corresponding active cells in each one of the plurality of threads. A multi-threaded memory system is also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.